The present invention relates to an apparatus and method for checking for faults in the input/output portion of a memory device and in particular to an apparatus and method for checking programmable read only memories to locate hardware faults.
In the manufacture of memory devices, it is typically desired to test the memory devices for faults before delivering or selling the memory devices. One type of memory which is typically tested is read only memory. This is a memory which is designed so that, in normal use, its contents can be read but cannot be written to or changed. A programmable read only memory (PROM) is a memory which, typically, can be written to once, i.e., in which it is possible to electronically change the state of a given memory cell (i.e., the unit of memory which is in either a first or second state, storing a "1" or a "0") from its erased state to the opposite state but in which a subsequent erasing of the programmed memory cell is not done during normal operation (other than EEPROMs). The writing of data to a cell of the PROM is called "programming". Typically, a PROM cell is programmed using voltages higher than those used in addressing and reading a cell.
One class of PROMs permits erasing of programmed cells but requires special procedures for erasing and thus does not permit erasing during normal, routine use of the memory. These memories are referred to as an erasable programmable read only memories (EPROM). In some types of EPROMs, data programmed or stored in the memory can be erased by exposing the cells to light, typically ultraviolet light. These memories are manufactured in a package which includes a window, typically a quartz window, to permit transmission of ultraviolet light. Windowed EPROMs are particularly useful during development because the memory can be reprogrammed to correct programming errors and the like. One difficulty with windowed EPROMs is the relatively high cost of producing the windowed packages. So it is economically advantageous to substitute windowless EPROMs, for windowed EPROMs, in products, after the software development phase is completed. Windowless EPROMs are sometimes referred to as one-time programmable (OTP) EPROMs. This term is something of a misnomer, since being windowless, the memory, once packaged, is not erasable.
Array devices that have an array of memory cells such as read only memories are sold as stand-alone chips, as well as being provided on chips which include circuitry in addition to the memory block. This additional circuitry may include data input devices and data output devices associated with the memory, other than standard data input and data output pins. See FIG. 9. In general, input circuitry refers to the Input Device Block 510 and Memory Input Datapath 512. Input Device Block 510 refers to the on-chip input devices which provide data to be written to the EPROM 514 (for example, Universal Asynchronous Receiver-Transmitter (UART), input pins, input register, etc.). Memory Input Datapath 512 selects and receives the data, and sends it to the array through bitlines 516 for the purpose of writing the data into array (which for an EPROM can include multiplexers (mux), an internal data input bus, a Data Program Block, etc.). In general, Data Output Circuitry refers to the Output Device Block 518 and Memory Output Datapath 522. Output Device Block refers to the on-chip output devices receiving data read from the EPROM 514 (such as data output pins, UART, etc.). Memory Output Datapath 522 receives the data being read out from the memory array, transfers to the internal data output bus of the memory, and selects and sends data to an output device 518. Memory Output Datapath for an EPROM can include an internal data output bus, sense amps, drivers, etc. EPROMs, for example, can include an input circuit which receives data through its input pins from an external data bus, in a manner well known in the art. Similarly, EPROMs can include an output circuit which during a read receives data from the array and outputs data through its output pins to an external databus, in a manner well known in the art. EPROMs can also be provided on multi-function or general function chips as an embedded EPROM. In this case, the EPROM input and output circuits may receive and output data from and to an on-chip bus, and there could be multiple input devices and output devices connected to this on-chip bus, as described above. In any case, it is often desired to determine whether the input/output circuitry associated with the EPROM is properly functioning. FIG. 9 shows Input Device Block 510, Memory Input Datapath 512, Output Device Block 518, and Memory Output Datapath 522 for a general case of a microcontroller with embedded EPROM 524. In some cases, at least some of the data input devices and data output devices are included in the input/output circuitry which needs to be tested using this apparatus and method. Thus, associated input/output circuitry refers to the part of memory input/output datapath and input/output devices testable using the methodology described here.
In the special case of OTP EPROMs, there are certain difficulties in testing the I/O circuitry. This can best be understood by describing how the testing of I/O circuits in normal or "windowed" EPROMs is conducted. Although a number of testing methodologies for I/O circuits of windowed EPROMs are available, the testing used according to previous schemes has involved writing data to at least some of the memory cells in the normally-used array. This can be done in the context of windowed EPROMs, since, following such a programming of cells in the array, the EPROM can be erased to permit the desired final programming to be placed into the memory array. Even with windowed EPROMs, this procedure has the undesirable characteristic that erasing the arrays can be undesirably time-consuming.
This type for testing is infeasible of OTP devices since cells that are programmed for a testing purpose cannot thereafter be erased to permit insertion of the desired program into the memory. In many commercially available OTP EPROMs, a number of additional EPROM cells are provided, in addition to the normal array. These additional cells are not accessed during normal operation, and, are exclusively for the purpose of testing certain functions including functions of the input/output circuit. This approach, however, has the limitation that the input circuit test cannot be fully repeated using the same set of additional cells, since it depends on programming the additional cells which cannot, thereafter, be erased. Also, using this approach, for an output circuit test, a large number of additional EPROM cells may be needed, depending on the output circuit to be tested. Because the input circuit testing is not fully repeatable it cannot be used to, for example, do an initial test, to subject the part to a dynamic life test or, for example, temperature or electronic environmental stresses, and subsequently perform another input circuit test. Furthermore, additional rows and columns used only for testing purposes reduce the area of the chip available for normal function memory and raises the cost of the device.
The problem is particularly acute in complex circuits, such as micro-controllers or other IC's with embedded EPROMs. Whereas simple EPROM chips, in which data pins are the only source of data, can be checked by, for example, writing and reading Reed-Muller codes and their negations as described in "Functional Testing of EPROMs, "Pawlowski, et al., IEEE Journal of Solid State Circuits, V. SC-19, No. 2, April, 1984, complex IC's with embedded EPROMs having multiple sources of data typically require much more complex data test patterns. Thus, in devices where the data cannot be erased, such complex test patterns require providing a large number of extra memory cells adding to the cost of the EPROM array. Complexity of the necessary test data patterns can arise from such factors as the multiplicity and complexity of the data input and output devices. Complex data input and output circuits require complex patterns to detect functional faults. A number of test patterns may be needed to write and read data test patterns at different temperatures, voltages, frequencies, etc. to fully evaluate a complex circuit.
Accordingly, it would be useful to provide a test for OTP EPROM to detect as many I/O circuit faults as feasible without requiring additional rows and columns dedicated to these tests. It would also be useful to provide an OTP EPROM in which as much I/O circuit testing as feasible can be repeatable without having to write to any EPROM cells, even for a first time.